PCI Express x1 PHY single-lane transceivers

For applications that use an ASIC or a low-cost FPGA to implement the MAC portion of the PCI Express protocol, NXP Semiconductors offers our PX1011 2.5-Gbps PCI Express PHY transceivers with 8-bit data PXPIPE interfaces. Available in very small, leaded and lead-free LFBGA-81 packages that measure only 9 x 9 x 1.05 mm, they offer features that ease layout, improve performance, and increase design flexibility.

NXP Semiconductors is the first discrete PCI Express PHY vendor to pass the PCI-SIG compliance tests. NXP Semiconductors has worked with multiple partners to perform comprehensive tests in multiple PC systems to ensure interoperability, compliance, and excellent throughput.

Fast, low-risk digital ASIC designs

Our PX1011 products makes ASIC development faster and less risky. By isolating the mixed-signal PHY functions in an external transceiver, they let the ASIC's digital functions migrate to the latest process technologies without impacting complex PHY operations.

Increased efficiency of low-cost FPGA designs

Low-cost, high-density FPGAs don't typically offer an on-chip PHY or SERDES. PX1011 products let designers use an inexpensive FPGA to create low-cost, flexible PCI Express applications that have customer-specific functions coded into the FPGA. The result is greater differentiation in a format that is easily scalable to high-volume, consumer-oriented applications.

Tiny package optimized for PCB layout

Our PX1011 PHYs come in the industry's smallest package, the LFBGA-81. Despite its tiny size, we have optimized the ease of layout by having 2 signal rings, thus requiring only two signal layers in the PCB design.

• PCI Express v1.0a compliant
• Passes PCI Express v1.1 informational jitter tests from PCI-SIG
• Suitable for ExpressCard applications
• One x1 physical lane
• Transmit or receive at 2.5Gbps
• Better than 1x10^-12 Bit Error Rate (BER)
• NXP PXPIPE (8-bit, 250-MHz) PHY-MAC interface
• FPGA-compatible SSTL2 signaling
• L0, L0s, L1 power management modes; partial support for L2, L3
• Leaded or lead-free LFBGA-81 package (9 x 9 x 1.05 mm)

PCI Express PHY NXP x1 PHY single-lane transceiver PX1011 © November 2007; English; Ordering code: 9397 750 16134

• More Interface PCI Express Literature

	PX1011A		PCI Express stand-alone X1 PHY; See PX1011B replacement
	PX1011B		PCI Express stand-alone X1 PHY with improved transmitter jitter and supply range
	PX1012A		PCI Express stand-alone X1 PHY for PLDA's IP core; See PX1011B replacement

The PCIe x1 PHY single-lane transceivers can be purchased from authorized distributors:

• Order Online at Avnet
• Order Online at Digi-Key

• Contact Arrow
• Contact Future

The Xilinx Spartan-3/3E FPGA has high-speed I/O capability and supports the 8-bit, 250-MHz PXPIPE interface used in the PX1011 products. Xilinx also supports our PX1011 products with their LogiCORE PCIe PIPE Endpoint IP.

• Xilinx LogiCORE PCIe PIPE Endpoint IP

Altera's Cyclone-II FPGA supports the PXPIPE interface with their PCI Express MegaCore.

• Altera's PCI Express Solutions

PLDA's PCI Express IP core supports the PX1011 products on both the Altera Cyclone II and Xilinx Spartan-3/3E FPGAs.

• PLDA PCI Express XpressLite IP Core

For more information about the IP vendors that support the NXP PXPIPE interface, please see our NXP NXP PXPIPE PHY/MAC Interface FAQ.

• Interface Frequently Asked Questions (FAQ)

• A Low-Cost Programmable PCI Express Solution (in Xcell Journal) (Q3 2005)
• A Programmable ExpressCard ExpressCard Solution (in Xcell Journa) (Q2 2006)
• AN10372 PXPIPE White Paper, V1 (Apr 30, 2005)
• AN10373 PCI Express PHY PCB Layout Guideline, V1 (Apr 30, 2005)
• AN10637 PX1011 SSTL_2 I/O termination and power dissipation, V1 (Nov 1, 2007)
• LPC32xx Common Driver Library (CDL), V1.10 (Nov 3, 2008)
• LPC32xx WinCE 6.0 Board Support Package (BSP), VBeta (Oct 30, 2008)
• New PCI Express Solution Simplifies Video Security Applications (in I/O Magazine) (Jan 2006)
• PCI Express (in Micro-Electronics; Nov 2004) (Nov 2004)
• PX1011A BSDL Boundary Scan File, V2 (May 24, 2006)
• PX1012A BSDL Boundary Scan File, V2 (May 24, 2006)
• The NXP/PLDA Programmable PCI Express Solution (in Xcell Journal) (Q3 2007)

• Refine These Support Documents Matches

• PCI Express PHY System Test Reports

• PX Circuit Simulation Models

• Xilinx Spartan-3 PCI Express Starter Kit Schematics
• Reference PCB Schematics for Low-Cost FPGA and PX1011 Products

• Xilinx/Avnet Spartan-3 PCI Express Starter Kit
• More Demonstration and Evaluation Boards

• Contact Us via Email

• PCI Express